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IR3841MPbF
Application Information
Design Example:
When an external resistor divider is connected to
the output as shown in figure 11.
Equation (5) can be rewritten as:
R 9 = R 8 ? ? ?
? .......... .......... .......... .... (8)
?
The following example is a typical application for
IR3841. The application circuit is shown on page
23.
? V ref
? V o ? V ref
?
?
V in = 12 V ( 13.2V max)
V o = 1.8 V
For the calculated values of R8
feedback compensation section.
and R9 see
I o = 8 A
Δ V o ≤ 54mV
F s = 600 kHz
Enabling the IR3841
IR3841
IR3624
Fb
V OU T
R 8
R 9
As explained earlier, the precise threshold of
the Enable lends itself well to implementation of
a UVLO for the Bus Voltage.
V in
Fig. 11. Typical application of the IR3841 for
programming the output voltage
Soft-Start Programming
The soft-start timing can be programmed by
IR3841
Enable
R 1
R 2
selecting the soft-start capacitance value. From
(1), for a desired start-up time of the converter,
the soft start capacitor can be calculated by
using:
C SS ( μ F ) = T start ( ms ) × 0.02857 .......... (9)
= V EN = 1.2 .......... (5)
V in (min) *
R 2 = R 1
V EN
V o = V ref ? ? ? 1 + 8 ? ? .......... .......... .......... .....(7)
For a typical Enable threshold of V EN = 1.2 V
R 2
R 1 + R 2
.......... (6)
V in( min ) ? V EN
For a V in (min) =10.2V, R 1 =4.99K and R 2 =750 ohm
is a good choice.
Programming the frequency
For F s = 600 kHz, select R t = 23.7 k ? , using
Table. 1.
Output Voltage Programming
Output voltage is programmed by reference
voltage and external voltage divider. The Fb pin
is the inverting input of the error amplifier, which
is internally referenced to 0.7V. The divider is
ratioed to provide 0.7V at the Fb pin when the
output is at its desired value. The output voltage
is defined by using the following equation:
? R ?
? R 9 ?
06/18/09
Where T start is the desired start-up time (ms).
For a start-up time of 3.5ms, the soft-start
capacitor will be 0.099 μ F. Choose a 0.1 μ F
ceramic capacitor.
Bootstrap Capacitor Selection
To drive the Control FET, it is necessary to
supply a gate voltage at least 4V greater than
the voltage at the SW pin, which is connected
the source of the Control FET . This is achieved
by using a bootstrap configuration, which
comprises the internal bootstrap diode and an
external bootstrap capacitor (C6). The operation
of the circuit is as follows: When the lower
MOSFET is turned on, the capacitor node
connected to SW is pulled down to ground. The
capacitor charges towards V cc through the
internal bootstrap diode, which has a forward
voltage drop V D . The voltage V c across the
bootstrap capacitor C6 is approximately given as
V c ? V cc ? V D .......... .......... ...... (10)
When the upper MOSFET turns on in the next
cycle, the capacitor node connected to SW rises
to the bus voltage V in . However, if the value of
C6 is appropriately chosen,
17
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